DC-WG: RE: DC-WG/SLDL: Agenda for 1/12 teleconference

Steve.Grout@sematech.org
Tue, 12 Jan 1999 10:17:01 -0600

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--Boundary_(ID_boNMOLyIxiW0Ryoi4jyDqg)
Content-type: text/plain; charset=iso-8859-1

Mark - re the status of my generating constraints definitions
for boundary parasitics, I attach an .rtf of a new edition
though still incomplete document, in the belief it will help to
get feedback on both the definitions that I have completed so
far, as well as the grouping of the terms.

It is coming together though I still spend a lot of time simply
rewriting and re-sorting them. The formatting now is per your
template (actually I still cheat slightly in that the matrix
is portrait and not landscape so I can edit in a window more
easily.) Note that I am continuing to carry the Ambit strawman
definitions as indented and as-is for reference by any reviewers

It IS coming together steadily now and I spend an hour or better on
it each evening.

I feel I am on the downhill now and should complete it by next Tuesday.

Please tell me if you were able to successfully read the attached file.
I would also greatly appreciate anyone's feedback on my approach to
the definitions, especially the main semantic definition. I would also
of course appreciate feedback on any other boundary parasitics that
this section should address.

Regards,
--Steve Grout
Sematech

>
> --
> Mark Hahn phone:
> (408) 428-5399
> Architect, Deep Submicron Business Unit fax:
> (408) 428-5959
> Cadence Design Systems email:
> mhahn@cadence.com
>

--Boundary_(ID_boNMOLyIxiW0Ryoi4jyDqg)
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\cellx8645\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 6\cell =
1/5/99\cell Steve Grout\cell Continued entering definitions for =
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\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 2\cell =
\cell Steve Grout\cell=20
2d pass list of objects, identify objects with Ambit C/L strawman =
definitions, copied in available Ambit definitions, and adding other =
definitions. Began to define both commands and design objects targeted =
by the commands.\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {SG pass 1\cell =
\cell Steve Grout\cell First pass of Parasitic Boundary conditions =
\endash=20
discussion of requirements, first list of objects to be defined.\cell =
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Mark Hahn\cell Initial Creation\cell }\pard\plain =
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\par 1.4.1.3.2\tab Input Port Internal Capacitance Limit\tab =
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\par 1.4.1.3.6\tab Input Port Lumped RC parasitic model\tab =
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}{\fldrslt {\lang1024 15}}}{\lang1024=20
\par 1.4.1.3.7\tab Input Port Distributed Hierarchical Boundary =
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\par 1.4.1.3.8\tab Unterminated (Open Circuit) Interface Input Port =
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\par 1.4.1.3.9\tab Terminated (Loaded) Instance (Occurrence) Input Port =
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\par }\pard \s39\li600\widctlpar\tx1818\tqr\tx8630\adjustright =
{\lang1024 1.4.1.3.10\tab Distributed R-C Input Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646130 \\h }{\lang1024 =
{\*\datafield=20
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\par 1.4.1.3.11\tab Distributed R-C-L Input Port Parasitics\tab =
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{\*\datafield=20
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\par 1.4.1.3.12\tab Distributed R-C-L-M Input Port Parasitics\tab =
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{\*\datafield=20
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\par }\pard\plain \s37\li200\widctlpar\tx1200\tqr\tx8630\adjustright =
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\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
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\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
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\lang1024=20
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{\lang1024 22}}}{\lang1024=20
\par }{\lang1024\cgrid0 1.4.2.1.6}{\lang1024 \tab }{\lang1024\cgrid0 =
set_fanout_load_limit}{\lang1024 \tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646140 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340030000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par 1.4.2.1.7\tab Output Port External Fanout m <redundant?>\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646141 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340031000000}}}{\fldrslt {\lang1024 =
23}}}{\lang1024=20
\par }\pard\plain \s38\li400\widctlpar\tx1400\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2\tab Output Port Internal Implementation =
Constraints\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646142 =
\\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340032000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2.1\tab Output Port Equivalent Custom Wire =
Load\tab }{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646143 \\h =
}{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340033000000}}}{\fldrslt {\lang1024 =
24}}}{\lang1024=20
\par 1.4.2.2.2\tab Equivalent Custom Wire Load Mode (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646144 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340034000000}}}{\fldrslt {\lang1024 =
25}}}{\lang1024=20
\par 1.4.2.2.3\tab Specified Wire Load Model (Ambit)\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646145 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340035000000}}
}{\fldrslt {\lang1024 25}}}{\lang1024=20
\par 1.4.2.2.4\tab Output Port Drive Capability\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646146 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340036000000}}
}{\fldrslt {\lang1024 26}}}{\lang1024=20
\par 1.4.2.2.5\tab Cell (Block) Drive (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646147 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340037000000}}
}{\fldrslt {\lang1024 26}}}{\lang1024=20
\par 1.4.2.2.6\tab Drive resistance (Ambit)\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646148 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340038000000}}}{\fldrslt {
\lang1024 27}}}{\lang1024=20
\par }\pard\plain \s40\li800\widctlpar\tx2067\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024\cgrid0 1.4.2.2.6.1}{\lang1024 \tab =
}{\lang1024\cgrid0 set_drive_resistance}{\lang1024 \tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646149 \\h }{\lang1024=20
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100340039000000}}}{\fldrslt {\lang1024 =
28}}}{\lang1024=20
\par }\pard\plain \s39\li600\widctlpar\tx1717\tqr\tx8630\adjustright =
\fs20\cgrid {\lang1024 1.4.2.2.7\tab Available Drive\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646150 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350030000000}}}{\fldrslt {\lang1024 =
28}}}{\lang1024=20
\par 1.4.2.2.8\tab Output port Drive Strength:\tab }{\field{\*\fldinst =
{\lang1024 PAGEREF _Toc440646151 \\h }{\lang1024 {\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350031000000}}
}{\fldrslt {\lang1024 29}}}{\lang1024=20
\par 1.4.2.2.9\tab Output Port Internal Capacitance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646152 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350032000000}}
}{\fldrslt {\lang1024 29}}}{\lang1024=20
\par }\pard \s39\li600\widctlpar\tx1818\tqr\tx8630\adjustright =
{\lang1024 1.4.2.2.10\tab Output Port Internal Capacitance Limit\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646153 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350033000000}}}{\fldrslt {\lang1024 =
30}}}{\lang1024=20
\par 1.4.2.2.11\tab Effective Drive Internal Capacitance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646154 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350034000000}
}}{\fldrslt {\lang1024 30}}}{\lang1024=20
\par 1.4.2.2.12\tab Effective Drive Internal Resistance\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646155 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350035000000}}
}{\fldrslt {\lang1024 31}}}{\lang1024=20
\par 1.4.2.2.13\tab Equivalent Custom Wire Drive - ???\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646156 \\h }{\lang1024 =
{\*\datafield =
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350036000000}}
}{\fldrslt {\lang1024 32}}}{\lang1024=20
\par 1.4.2.2.14\tab Output Port Internal Lumped RC parasitic model\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646157 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350037000000}}}{\fldrslt {\lang1024 =
32}}}{\lang1024=20
\par 1.4.2.2.15\tab Output Port Distributed Hierarchical Boundary =
Parasitics (Impedance)\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646158 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350038000000}}}{\fldrslt {\lang1024 =
33}}}{\lang1024=20
\par 1.4.2.2.16\tab Unterminated (Open Circuit) Interface Output Port =
Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 PAGEREF =
_Toc440646159 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100350039000000}}}{\fldrslt {\lang1024 =
33}}}{\lang1024=20
\par 1.4.2.2.17\tab Terminated (Loaded) Instance (Occurrence) Output =
Port Parasitic (impedance) model\tab }{\field{\*\fldinst {\lang1024 =
PAGEREF _Toc440646160 \\h }{\lang1024 {\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360030000000}}}{\fldrslt {\lang1024 =
34}}}{\lang1024=20
\par 1.4.2.2.18\tab Distributed R-C Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646161 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360031000000}}}{\fldrslt {\lang1024 =
35}}}{\lang1024=20
\par 1.4.2.2.19\tab Distributed R-C-L Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646162 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360032000000}}}{\fldrslt {\lang1024 =
35}}}{\lang1024=20
\par 1.4.2.2.20\tab Distributed R-C-L-M Output Port Parasitics\tab =
}{\field{\*\fldinst {\lang1024 PAGEREF _Toc440646163 \\h }{\lang1024 =
{\*\datafield=20
08d0c9ea79f9bace118c8200aa004ba90b02000000080000000e0000005f0054006f0063=
003400340030003600340036003100360033000000}}}{\fldrslt {\lang1024 =
36}}}{\lang1024=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
}}\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\kerning28 =
\sect }\sectd =
\marglsxn1440\margrsxn2160\margtsxn1613\margbsxn1685\psz1\sbkcol\linex0\=
colsx0\titlepg\sectdefaultcl=20
{\*\bkmkstart clock}{\*\bkmkstart parasitics}{\*\bkmkstart =
_Toc422101856}{\*\bkmkstart _Toc440646101}{\*\bkmkend clock}{\*\bkmkend =
parasitics}{\listtext\pard\plain\s1 \b\fs20\kerning28\cgrid =
\hich\af0\dbch\af0\loch\f0 1\tab}\pard\plain=20
\s1\fi-432\li432\sb240\sa60\keepn\pagebb\widctlpar\brdrb\brdrs\brdrw30\b=
rsp20 \jclisttab\tx432\ls38\outlinelevel0\adjustright =
\b\fs28\kerning28\cgrid {\fs20 Design Constraints \endash Especially =
Timing Constraints Driving Synthesis
{\*\bkmkend _Toc440646101} {\*\bkmkend _Toc422101856}
\par {\*\bkmkstart _Toc440646102}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.1\tab}}\pard\plain =
\s2\qj\fi-576\li576\sb240\keepn\widctlpar\jclisttab\tx576\ls38\ilvl1\out=
linelevel1\adjustright \b\cgrid {(See ParasaticsDiscussion04sg)
{\*\bkmkend _Toc440646102}
\par {\*\bkmkstart _Toc440646103}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.2\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc440646103}
\par {\*\bkmkstart _Toc440646104}{\listtext\pard\plain\s2 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.3\tab}(See =
ParasaticsDiscussion04sg){\*\bkmkend _Toc440646104}
\par {\listtext\pard\plain\s2 \b\cgrid \hich\af0\dbch\af0\loch\f0 =
1.4\tab}\page {\*\bkmkstart _Toc440646105}Hierarchical Parasitic =
Boundary Conditions{\*\bkmkend _Toc440646105}=20
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {This =
section defines constraint terms for hierarchical parasitic boundary =
conditions. =20
\par Note that, when available and where applicable, the related term =
from the Ambit constraint strawman is also included for reference.
\par {\*\bkmkstart mark}{\*\bkmkstart _Toc432826548}{\*\bkmkstart =
_Toc434042497}{\*\bkmkstart _Toc434061598}{\*\bkmkstart =
_Toc440646106}{\*\bkmkend mark}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1\tab}}\pard\plain=20
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls42\ilvl2\outlinelevel2\adjustright \b\cgrid {Port General Parasitic =
Boundary Conditions{\*\bkmkend _Toc440646106}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following parasitic constraint definitions apply to both input and =
output ports.}{\cs46\super \chftn {\footnote \pard\plain =
\s45\qj\sb120\widctlpar\adjustright \fs20\cgrid {\cs46\super \chftn }
{ Note: The Ambit }{constraint}{ strawman stated several port or =
boundary constraints from the point of view of applying to either input =
or output ports. }}}{
\par {\*\bkmkstart _Toc440646107}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Port Capacitance
{\*\bkmkend _Toc440646107}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance=20
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the =
capacitance external to the cell, block or design=20
based on input and output loading from other ports and nets connected =
to the ports of the current module.
\par The total }{\cgrid0 external }{\cgrid0 capacitance at any port is =
the sum of the external port and net capacitances that the port is =
connected to in the design hierarchy. Note that this capacitance does =
not include any capacitance contribution of=20
the port itself or any contribution from the port and net lying behind =
the port inside the cell.
\par For an input port, the Port Capacitance refers to the capacitance =
contributed by all the ports of the drivers that may be connected to =
the external hierarchical net, and the capacitance of the other loads =
on the external hierarchical net.=20
\par For output ports, the port capacitance refers to the capacitance =
of all the external sinks, and/or }{\cgrid0 external }{\cgrid0 drivers, =
for the case of a multiply-driven net, that are connected to the =
external hierarchical net. This capacitance includes=20
capacitance contributions of other input ports and of any other =
external drivers connected to the hierarchical net.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or output ports of a cell or =
cell instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Capacitance of the connected net, =
its own capacitance, and the capacitances of the ports connected to the =
net
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name or list\cell List of Identifier\cell \cell Identifies the ports on =
the target cell or cell instance=20
that will have the capacitance value.\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell or =
cell instance\cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell Name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10170\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Sum of the }{capacitance =
}{contributions of the ports and net of the external hierarchical =
network connected to the target port\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc440646108}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.1.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar
\jclisttab\tx1152\ls38\ilvl5\outlinelevel5\adjustright \i\fs22\cgrid =
{\cgrid0 Reference only: set_port_capacitance }{\fs20 =
(Ambit){\*\bkmkend _Toc440646108}
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f18\cf1\cgrid0 Command}{\f18\cf1\cgrid0 : }{\f6\fs16\cf1\cgrid0 =
set_port_capacitance
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 =
Syntax:}{\b\f1\fs18\cgrid0 :}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance <capacitance> <port_list>
\par }{\b\cgrid0 Description: }{\cgrid0 The }{\f6\fs16\cgrid0 =
set_port_capacitance }{\cgrid0 command specifies the capacitance =
external to the design based on input and output loading from other =
ports and nets connected to the ports of the current module.

\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid {\cgrid0 =
The capacitance at any port is the sum of the external port =
capacitances the port is connected to. For an input port the
port capacitance refers to the capacitance of all the ports of the =
driver that are connected to the net and the capacitance of the other =
loads on the net. For output ports, the port capacitance refers to the =
capacitance of all the external sinks, or exte
rnal drivers, for the case of multiply-driven net, that are connected =
to the net as well as the capacitance of the input port of any other =
external drivers
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Arguments: =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f19\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par port_list }{\i\f19\cgrid0 \emdash }{\f1\fs18\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Options:}{\cgrid0 =
None
\par }{\b\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb240\widctlpar\adjustright {\b\cgrid0 Design Database: =
}{\cgrid0 None
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_current_module, set_port_capacitance_limit
\par }{\b\cgrid0 Examples: }{\cgrid0 This command sets a 3.2 =
capacitance on all output ports of the current module whose names match =
dbus at the start The unit of capacitance will be the same as the unit =
of capacitance used in the library.
\par }\pard \fi720\sb120\widctlpar\adjustright {\f2\cgrid0 =
set_port_capacitance 3.2 [find -port \endash output }{\f2\cf1\cgrid0 =
bus*]
\par {\*\bkmkstart _Toc440646109}{\listtext\pard\plain\s5 \b\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {\cgrid0=20
Port Capacitance Limit{\*\bkmkend _Toc440646109}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the maximum =
value of the }{\fs18\cgrid0 capacitance}{\cgrid0 external to the =
target=20
port based on the sum of all the capacitance of all input =
}{\fs18\cgrid0 and output ports and net that are hierarchically =
connected to the target port of the target cell. This constraint =
}{\cgrid0 may be used to override global capacitance constraints.

\par This constraint may be specified on a cell interface =
(input}{\f18\cgrid0 and output) port of a design hierarchy, including =
}{\cgrid0 on a top }{\f18\cgrid0 level input and/or output port. This =
sets the constraint that the total capacitances (i.e.,
net or wire capacitance and port capacitance) of hierarchical nets =
attached to the ports in the port list do not exceed the specified =
maximum value of capacitance
. This constraint may be used to override the default port or net =
capacitance limit constraint that may be separately set by the =
}{\f6\fs16\cgrid0 Global_Capacitance_Limit constraint}{\f1\fs18\cgrid0 =
.
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {
\par }\pard =
\s30\li288\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright {\b =
Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or output ports of a cell or =
cell instance=20
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for =
capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target Port =
name or list\cell List of Identifier\cell The target port(s) must exist =
within target cell\cell=20
Identifies all the ports that are to have the port capacitance limit =
value\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell or cell instance\cell Identifier
\cell Cell must exist in the target design hierarchy\cell Name of the =
cell (if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 \trbrdrb
\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Capacitance =
limit value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell Maximum value of capacitance of the =
ports and net external to the target ports\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard=20
\qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646110}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_capacitance_limit }{(Ambit)}{\cgrid0 =
{\*\bkmkend _Toc440646110}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid =
{\b\f18\cgrid0 Command:}{\f18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit
\par }{\b\fs18\cgrid0 Syntax:}{\f1\fs18\cgrid0 }{\cgrid0 =
set_port_capacitance_limit <capacitance> <port_list>
\par }{\b\fs18\cgrid0 Description:}{\cgrid0 The }{\fs16\cgrid0 =
set_port_capacitance_limit }{\cgrid0 command specifies the limit on the =
}{\fs18\cgrid0 capacitance}{\cgrid0 (maximum value) external to the =
design based on input }{\fs18\cf1\cgrid0=20
and output loading from other ports and nets connected to the ports of =
the current module. }{\cf1\cgrid0 It is used to override design rule =
constraints set by the global attribute
\par }{\b\fs18\cgrid0 set_capacitance_limit:}{\cgrid0 These =
constraints can be specified on top }{\f18\cf1\cgrid0 level input and =
output ports. It sets the constraint that the total capacitances (i.e., =
wire capacitance a
nd pin capacitance) of nets attached to the ports in the port list do =
not exceed the specified capacitance limit. This command overrides the =
default limit set by the }{\f6\fs16\cf1\cgrid0 =
set_global_capacitance_limit }{\f18\cf1\cgrid0 command}{
\f1\fs18\cf1\cgrid0 .
\par }{\b\fs18\cgrid0 Arguments:}{\cgrid0 =20
\par }\pard \fi720\sb120\widctlpar\adjustright {\f6\fs16\cgrid0 =
capacitance }{\i\f19\cgrid0 \emdash }{\cgrid0 Capacitance value.
\par }\pard \fi720\sb120\nowidctlpar\adjustright {\f6\fs16\cf1\cgrid0 =
port_list }{\i\f19\cf1\cgrid0 \emdash }{\f1\fs18\cf1\cgrid0 List of =
ports.
\par }\pard \sb120\widctlpar\adjustright {\b\fs18\cgrid0 Options:}{\cgri=
d0 None
\par }{\b\fs18\cgrid0 Attributes:}{\cgrid0 capacitance_limit
\par }\pard \sb120\nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par }\pard \sb120\widctlpar\adjustright {\b\cgrid0 Related =
Commands:}{\cgrid0 set_fanout_load_limit, }{\f1\fs18\cf1\cgrid0 =
set_slew_limit, set_port_capacitance
, set_num_external_sources, set_num_external_sinks, do_derive_context, =
do_time_budget, set_global capacitance_limit
\par }{\b\cgrid0 Examples:}{\f1\cgrid0 }{\cgrid0 =
set_port_capacitance_limit 5.0 [find -port dbus*]
\par {\*\bkmkstart _Toc440646111}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.1.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Global Capacitance Limit{\*\bkmkend _Toc440646111}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Global Capacitance Limit
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: }{\cgrid0 Specifies the default =
maximum value of the }{\fs18\cgrid0 capacitance}{\cgrid0 is defined to =
exist external to the target port
}{\fs18\cgrid0 . }{\cgrid0=20
\par This constraint may be specified on a cell interface =
input}{\f18\cgrid0 or output port of a design hierarchy, including =
}{\cgrid0 on a top }{\f18\cgrid0 level input port. This defines the =
constraint of the default maximum capacitance=20
(i.e net or wire capacitance and port capacitance) of hierarchical =
network external to the target ports in the port list. This constraint =
may be overriden by defining a port or net capacitance limit =
constraints.}{\f1\fs18\cgrid0=20
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input or Output Port of a cell =
definition interface, or cell instance interface
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Design requirements for default =
maximum capacitance loading of an input or output port
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10350\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10080\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Default =
External }{Capacitance value\cell Floating \endash farad\cell=20
Zero or greater value in farads. ISO/IEEE postfix multiplier may be =
used, e.g., uF, nF, pF, etc.\cell }{Default maximum }{value of =
capacitance of the ports and net external to the target ports\cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {
\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646112}{\listtext\pard\plain\s3 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.2\tab}}\pard\plain =
\s3\qj\fi-720\li720\sb120\keepn\widctlpar\jclisttab\tx720\jclisttab\tx78=
0\ls42\ilvl2\outlinelevel2\adjustright \b\cgrid {
Input Port Specific Parasitic Boundary Conditions{\*\bkmkend =
_Toc440646112}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {The =
following constraint definitions are specific to input ports.
\par {\*\bkmkstart _Toc440646113}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx86=
4\ls38\ilvl3\outlinelevel3\adjustright \b\cgrid {
Input Port External Environment Constraints{\*\bkmkend _Toc440646113}
\par }\pard\plain \s17\sb120\widctlpar\adjustright \fs20\cgrid =
{{\*\bkmkstart InputPortExternal}{\*\bkmkend InputPortExternal}
The following are descriptions and constraints found at the input ports =
of the external implementation or instance of block when it is used =
within a design hierarchy. That is, these constrai
nts describe or prescribe those properties of the environment =
surrounding the use of an input port of an instance of a block. These =
constraints are part of the characteristics of what may or should =
happen at or near the input port of an instance of a bloc
k when later signals propagate to the input port via the surrounding =
interconnect at the next level of the design hierarchy.
\par {\pntext\pard\plain\s44 \f3\fs20\cgrid \loch\af3\dbch\af0\hich\f3 =
\'b7\tab}}\pard\plain =
\s44\qj\fi-360\li360\sb120\widctlpar\jclisttab\tx360{\*\pn =
\pnlvlblt\ilvl0\ls30\pnrnot0\pnf3\pnstart1\pnindent360\pnhang{\pntxtb =
\'b7}}\ls30\adjustright \fs20\cgrid {
(Note: In CHDStd hierarchical representation, these input port external =
environment constraints are properties of an instance port (usage_port) =
of the block instance and comprise part of the block instance =
(usage_box) interface definition.)
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {
\par {\*\bkmkstart _Toc440646114}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.1\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Equivalent External Sources{\*\bkmkend _Toc440646114}=20
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Equivalent External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the number of ports =
that are or may be connected to
the target port and are able to drive it. The number is stated in =
terms of a typical strength driving port. }{\cgrid0 This number is =
factored into the wire capacitance and wire resistance estimation done =
for the net connected to the target port.}{

\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Cell Parasitics Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fanin
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell Restrictions\cel=
l Semantics\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid =
{\row }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell Identifies =
the in
put port on the target cell or cell instance \cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Cell identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10147\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number external ports\cell Float\cell \cell Number of =
equivalent ports\cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row {\*\bkmkstart =
_Toc440646115}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.2\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar
\jclisttab\tx1008\ls38\ilvl4\outlinelevel4\adjustright \b\fs22\cgrid =
{Number External Sources (Ambit \endash =
num_external_sources){\*\bkmkend _Toc440646115}
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Number External Sources
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: =20
Specifies the number of actual external ports that are or may be =
connected to the target port of a cell or cell instance and are driving =
it. }{\cgrid0 This number is factored i
nto the wire capacitance and wire resistance estimation done for the =
net connected to the target port.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{Hierarchical connectivity fan-in
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell Input or bi-directional port\cell=20
Identifies the input port on the target cell or cell instance \cell =
}\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid =
{Target cell \cell Identifier\cell=20
Cell must exist in the target design hierarchy\cell name of the cell =
(if the top cell) or cell instance\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10=20
\trbrdrh\brdrs\brdrw10 \clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx10147\pard\plain \s17\sb120\keep\widctlpar\intbl\adjustright =
\fs20\cgrid {Number external ports\cell Float\cell \cell Number of =
actual or potential ports external to the target port
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\pard \qj\sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646116}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.2.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0 Reference only=20
\endash set_num_external_sources{\*\bkmkend _Toc440646116}(Ambit)
\par }\pard\plain \sb120\nowidctlpar\adjustright \fs20\cgrid =
{\b\f18\cf1\cgrid0 Command: }{\f6\fs16\cf1\cgrid0 =
set_num_external_sources
\par }{\b\cf1\cgrid0 Syntax: }{\cf1\cgrid0 set_num_external_sources =
<num_sources> <port_list>
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 Description: =
}{\cf1\cgrid0 The set_nu
m_external_sources command can be specified on top level input and =
output ports. This command sets the constraint that the number of =
external sources specified by the command are connected to the ports in =
the port list. This number is factored into the wi
re capacitance and wire resistance estimation done for the port nets =
using the wire load models.
\par }{\b\cf1\cgrid0 Arguments:}{\b\f1\fs18\cf1\cgrid0 =
}{\f1\fs18\cf1\cgrid0 num_sources \emdash Number of external sources
\par }\pard \sb120\nowidctlpar\adjustright {\f1\fs18\cf1\cgrid0 =
port_list \emdash List of ports
\par }\pard\plain \s18\nowidctlpar\adjustright \b\f4\fs20\cf1\cgrid =
{\f0\cgrid0 Options:
\par Attributes:
\par Design Database:
\par Related Commands:
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\b\cf1\cgrid0 =
Examples:}{\b\f1\fs18\cf1\cgrid0 }{\f6\fs18\cf1\cgrid0 =
set_num_external_sinks
\par }\pard \fi720\nowidctlpar\adjustright {\f6\fs18\cf1\cgrid0 =
set_port_capacitance
\par do_derive_context
\par do_time_budget}{\f18\fs16\cf1\cgrid0=20
\par }\pard \sb120\widctlpar\adjustright {
\par {\*\bkmkstart _Toc440646117}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.3\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {
Input Port External Wire Load{\*\bkmkend _Toc440646117}
\par }\pard\plain \qj\sb120\widctlpar\adjustright \fs20\cgrid {(Derived =
from the Ambit definition)
\par }\pard\plain \s25\qj\sb240\keepn\widctlpar\adjustright =
\b\i\fs20\cgrid {Name: Port Wire Load
\par }\pard\plain =
\s28\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {Semantic definition: Specifies the wire load model =
that will be applied to a net that is connected to the target input or =
output=20
interface port (e.g., top level port) of a cell when the cell is =
instantiated in a design. The }{\cgrid0 specified wire load model =
information is used for wire capacitance and resistance estimation. If =
more than one port with this port_wire
_load assertion is connected to the net, then the worst-case of all the =
wire load model assertions shall be used in=20
estimating the wire capacitance and resistance for the net. The Library =
Name identifies the library that contains the specified wire load model
data. If the library is not specified, then the default wire load =
model information for the target technology shall be used.}{
\par }\pard\plain =
\s30\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Type}{\tab Parasitic Boundary Condition
\par }\pard\plain =
\s35\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Applies To}{\tab Input ports of a cell or cell =
instance
\par }\pard\plain =
\s33\li288\sb120\widctlpar\tx1980\tx4620\tx6060\tx9390\adjustright =
\fs20\cf1\cgrid {\b Depends On\tab }{None
\par }\pard\plain \s34\qj\li288\sb120\widctlpar\tx1980\adjustright =
\fs20\cgrid {\b Verified By}{\tab ERC
\par }\pard\plain \s31\li288\sb120\sa120\widctlpar\adjustright =
\b\fs20\cgrid {Parameters
\par }\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx2250\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw30\brdrcf1 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain =
\s18\nowidctlpar\intbl\adjustright=20
\b\f4\fs20\cf1\cgrid {\b0\cf0 Name\cell Value Type\cell =
Restrictions\cell Semantics\cell }\pard\plain =
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10=20
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx6547\clvertalt\clbrdrt
\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10147\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target port =
name\cell Identifier\cell \cell Identifies the port on the target cell =
or cell instance \cell }\pard\plain=20
\widctlpar\intbl\adjustright \fs20\cgrid {\row }\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Target cell =
\cell Identifier\cell Cell must exist in the target design =
hierarchy\cell name of the cell (if the top cell) or cell instance
\cell }\pard\plain \widctlpar\intbl\adjustright \fs20\cgrid {\row =
}\trowd \trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb \cellx10170\pard\plain=20
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Wire load =
model name\cell Identifier\cell Optional\cell Name of the Wire load =
model that is to optionally be applied to the target input port\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\trowd =
\trgaph108\trleft450\trbrdrt\brdrs\brdrw30\brdrcf1 =
\trbrdrb\brdrs\brdrw10 \trbrdrh\brdrs\brdrw10 =
\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx2250\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10=20
\cltxlrtb \cellx4008\clvertalt\clbrdrt\brdrs\brdrw10 =
\clbrdrb\brdrs\brdrw10 \cltxlrtb =
\cellx6547\clvertalt\clbrdrt\brdrs\brdrw10 \clbrdrb\brdrs\brdrw10 =
\cltxlrtb \cellx10170\pard\plain =
\s17\sb120\keep\widctlpar\intbl\adjustright \fs20\cgrid {Library name
\cell Identifier\cell Optional\cell Name of optional Library that =
contains the Wire load model. If the library is not identified, then =
the wire load model information of the technology shall be used.\cell =
}\pard\plain \widctlpar\intbl\adjustright=20
\fs20\cgrid {\row }\pard \qj\sb120\widctlpar\adjustright {
\par=20
\par {\*\bkmkstart _Toc440646118}{\listtext\pard\plain\s6 \i\fs22 =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.3.1\tab}}\pard\plain =
\s6\qj\fi-1152\li1152\sb240\sa60\widctlpar\jclisttab\tx1152\ls38\ilvl5\o=
utlinelevel5\adjustright \i\fs22\cgrid {\cgrid0=20
Reference only: set_port_wire_load{\*\bkmkend _Toc440646118}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {\b\cgrid0 =
Command:}{\f18\cgrid0 }{\cgrid0 set_port_wire_load
\par }\pard \widctlpar\adjustright {\b\cgrid0 Syntax:}{\f1\fs18\cgrid0 =
}{\cgrid0 set_port_wire_load ?-library <library_name>? <wire_load> =
}{\f6\fs16\cf1\cgrid0 <port_list>
\par }{\b\cgrid0 Description:}{\cgrid0 }{ }{\cgrid0 The =
set_port_wire_load command specifies the wire load for either =
}{\cf1\cgrid0=20
an input or output top level port of a design. The net connected to the =
port is associated with the specified wire load model, which is used =
for wire cap and resistance estimation. If a net i
s connected to more than one port with a set_port_wire_load assertion, =
then the worst wire load model is computed and used for the net. The =
library name indicates the location of the specified wire load model. =
If the library is not specified, then the wir
e load is located from the target technology (the default location).
\par }{\b\cgrid0 Arguments:}{\cgrid0=20
\par }{\b\cgrid0 Options:}{\cgrid0=20
\par }{\b\cgrid0 Attributes:}{\cgrid0=20
\par }\pard \nowidctlpar\adjustright {\b\fs18\cf1\cgrid0 Design =
Database:
\par Related Commands:}{\f1\fs18\cf1\cgrid0 set_wire_load, =
set_num_external_sinks
\par }{\b\fs18\cf1\cgrid0 Examples:
\par {\*\bkmkstart _Toc440646119}{\listtext\pard\plain\s5 \b\fs22\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.2.4\tab}}\pard\plain =
\s5\qj\fi-1008\li1008\sb240\sa60\widctlpar\jclisttab\tx1008\ls38\ilvl4\o=
utlinelevel4\adjustright \b\fs22\cgrid {Input Port Wire Load=20
{\*\bkmkend _Toc440646119}
\par }\pard\plain \sb120\widctlpar\adjustright \fs20\cgrid {See =
port_wire_load.
\par }\pard \sb120\nowidctlpar\adjustright {\f18\fs16\cf1\cgrid0=20
\par {\*\bkmkstart _Toc440646120}{\listtext\pard\plain\s4 \b\cgrid =
\hich\af0\dbch\af0\loch\f0 1.4.1.3\tab}}\pard\plain =
\s4\qj\fi-864\li864\sb120\keepn\widctlpar\jclisttab\tx780\jclisttab\tx